Expansion bus - Revision history

DavidCary: mention a few more influential game cartridge buses, etc.

2026-05-14T21:21:15Z

mention a few more influential game cartridge buses, etc.

DavidCary: fill in more details; link to related Open Circuits articles; etc.

2026-04-23T21:56:49Z

fill in more details; link to related Open Circuits articles; etc.

DavidCary: fill in more details on Grove, etc.

2025-08-27T00:34:48Z

fill in more details on Grove, etc.

DavidCary: fill in a few details, with references.

2024-02-29T05:11:06Z

fill in a few details, with references.

DavidCary: rough draft

2024-02-25T05:00:21Z

rough draft

New page

Expansion buses are designed to allow people to mix-and-match peripheral devices and CPUs.

== History ==

The earliest expansion buses
were more-or-less directly connected to the pins of a CPU.

Some early systems had a unified "system bus"
that both memory cards and peripherals plugged into,
leading to "memory-mapped I/O".
Typically a "system bus" is composed
of the address bus, the data bus, and the control bus,
and often also includes multiple pins dedicated to ground and power rails.

Later systems generally separate high-speed stuff
(the CPU, the RAM, on-board video (if any), graphics card slot (if any), and coprocessors (if any)) (the "Front-side bus") from slower speed stuff (expansion bus slots, off-board cables and ports).

There are two different reasons for this separation:
In low-cost microcontrollers, the cost of pins is a significant cost of the whole system,
so (a) we can use a much lower-cost packaging (far fewer pins)
if we don't expose the address bus or data bus outside the chip
(by putting all of the program Flash and data RAM on the same chip as the CPU)
(b) using a "narrower" bus to communicate with peripherals
also saves a bunch of pins in those peripherals,
making them cost less.
In high-end systems, the CPU, video, and RAM run much faster than peripherals,
so separating the busses allows the CPU to do dozens or hundreds of memory cycles
while waiting for a peripheral to handle a single expansion bus cycle.

== qwiic ==

SparkFun's [https://www.sparkfun.com/qwiic Qwiic Connect System] uses 4-pin JST connectors.
It's based on the [[I2C]] bus.

== UEXT ==

Universal EXTension (UEXT) is a connector layout which includes power and three serial buses:
Asynchronous, I2C, and SPI separately over 10 pins in a 2x5 layout.

== RC2014 bus ==

"RC2014 is a simple 8 bit Z80 based modular computer.
It was designed to be simple.
Simple to build, simple to understand, and simple to program."

* [https://rc2014.co.uk/ "RC2014"].
* [https://smallcomputercentral.com/documentation/specification-rc2014-bus/ "RC2014 bus"]
* [https://rc2014.co.uk/1377/module-template/ "RC2014 Module standard bus"]
* [https://groups.google.com/g/rc2014-z80 "RC2014-Z80"]
* [[stripboard]] with 0.1″ header sockets: [https://rc2014.co.uk/backplanes/veroboard-back-plane/ "Back Plane-Veroboard"]
* [https://smallcomputercentral.com/documentation/rc2014-bus/ "RC2014 BUS"]

== Backbone Bus ==

Backbone is a proposal for a backplane interconnect that supports multiple bus masters.<ref>
[https://hackaday.io/project/11928-backbone-bus "Backbone Bus"].
</ref>
Samuel A. Falvo II

== STEbus ==

* [https://en.wikipedia.org/wiki/STEbus Wikipedia: STEbus]
* [https://hackaday.io/project/11928-backbone-bus/log/200068-why-i-am-and-am-not-a-fan-of-stebus "Why I Am and Am Not a Fan of STEbus."].

== PC104 ==

The PC/104 standards
defines both [[form factor]]s and computer buses
allowing consumers to stack together boards from a variety of manufacturers
to produce a customized embedded system.

PC/104 boards are stacked on top of each other like LEGOs,
unlike nearly all other expansion buses.

The original PC/104 connectors
are electrically the same signals as the IBM PC/AT
but with a different, stacking connector.

== PATA ==

Parallel ATA (PATA)
is also electrically the same signals as the IBM PC/AT,
but with a different physical hardware -- PATA uses ribbon-cables and square header pins.

== Expansion bus design considerations ==

* latency (often *more* important than bandwidth)
* How far apart are the ends of the bus (length)?
* How many data bits to transfer per transaction (data bus width)?
* how many address bits to transfer per transaction (address bus width)?
* Dedicated 1 wire line for each address bit and and separate wire for each data bit (easier to test)? Or somehow multiplex 2 or more of those signals (lower cost)?
* How many peripheral devices can be plugged into the bus at the same time?
* How many controllers can be plugged into the bus at the same time? (A single controller and everything else are peripherals? Or multi-controller?)
* Can 2 identical peripherals be plugged into the bus at the same time, and how can software distinguish them?
* hot-pluggable?
* fault-tolerant?
* EMI/EMC
* Fixed, dedicated, unshared interrupt lines from each peripheral to the CPU? Or daisy-chained interrupt line?
* Fixed maximum number of peripherals per bus? Or daisy-chaining an arbitrary number of peripherals?
* What's the maximum fanout of the devices that drive the bus? Early TTL-based systems used chips with a typical max fanout of around 5, so "clever" techniques were required to support more than 5 peripherals. Modern high-speed systems often use point-to-point links (fanout of 1) for speed.
* Backplane? Motherboard? Stacking connectors? Ribbon cables? Something else?
* Off-the-shelf connectors available from second sources?
* Rugged connectors that are reliable for hundreds of plug/unplug cycles?
* [[stripboard]]/Veroboard with 0.1″ header sockets?
* bandwidth

For many years, the bandwidth (the number of bits we can shove across the bus per second)
seemed to be so important that we sacrificed many things to increase the bandwidth.
But surprisingly often, new systems are specifically designed for *lower* bandwidth
in order to regain some of the things that were sacrificed.

== Related ==

* [[Minimig Expansion]]
* [[Multi-purpose Embedded System]]
* [[Relay CPU]]
* [[Modules]]

* [https://github.com/tpycio/Backplane4 "Backplane 4+1 for RCBus"]
* [https://hackaday.io/project/183266-baffa-2-homebrew-microcomputer BAFFA backplane]
* What expansion bus does the N8VEM home brew Z80 computer project use?
* What expansion bus does the [https://hackaday.io/project/186398-hb6809-homebrew-computer "HB6809 Homebrew computer"] use?
* What expansion bus does the [https://hackaday.io/project/20377-firefly "Firefly: A Z80 Retrocomputing Development System"] use?
* What expansion bus does the [https://hackaday.io/project/166599-8-bit-in-style-the-pic18-computer "8-bit in style: the PIC18 computer... Base18"] use? (I see it's a 60 pin bus, including 24 address pins and 8 data pins).
* "Bread-Board friendly Q-bus extended" or BBQ-bus+" used by the [https://hackaday.io/project/67369-pdpii "PDPii PDP-11 compatible motherboard"] ?
* What expansion bus does the [https://hackaday.io/project/6025-skajntt "SkajNätt: An expandable computer system"] use?

@@ Line 82: / Line 82: @@
 (like many later video game cartridges)
 plugged into a socket that was directly wired to the CPU system bus.
 === expansion bus as separate from system bus ===
@@ Line 229: / Line 271: @@
 Another Nascom emulator is at http://www.nascomhomepage.com/#VirtualNascom .
 == Expansion bus design considerations ==

@@ Line 38: / Line 38: @@
 and the remaining cards
 could be put off until later.
 That first expansion bus
@@ Line 64: / Line 68: @@
 * [https://www.computer.org/csdl/magazine/co/1979/07/01658813/13rRUxYrbOU "This proposed standard eliminates many of the problems in the S-100 bus and upgrades it for 16-bit microprocessors."].
 * [http://www.s100computers.com/ "S100Computers... vintage S-100 bus based computers"]
 * [https://users.glitchwrks.com/~glitch/2011/09/01/debug-board "A Debug Board for the S-100 Bus"]
 * [https://retrocomputing.stackexchange.com/questions/tagged/s-100 "Questions tagged [s-100]"]
@@ Line 192: / Line 197: @@
 == RS485 ==

@@ Line 15: / Line 15: @@
 of the address bus, the data bus, and the control bus,
 and often also includes multiple pins dedicated to ground and power rails.
 The highly influential expansion bus of the
@@ Line 67: / Line 69: @@
 * [https://users.glitchwrks.com/~glitch/2018/07/02/reproducing-the-io2 "Reproduction S-100 Solid State Music IO-2 prototyping board"]
 * [https://www.pestingers.net/pdfs/other-computers/s100-bus-handbook-by-dave-bursky.pdf "The S-100 Bus Handbook"] by Dave Bursky.
 Gerald Anderson "Jerry" Lawson is known as the "father of the video game cartridge".
@@ Line 73: / Line 77: @@
 (like many later video game cartridges)
 plugged into a socket that was directly wired to the CPU system bus.
 Later systems generally separate high-speed stuff
@@ Line 93: / Line 99: @@
 SparkFun's [https://www.sparkfun.com/qwiic Qwiic Connect System] uses 4-pin JST connectors.
 It's based on the [[I2C]] bus.
 == UEXT ==
 Universal EXTension (UEXT) is a connector layout which includes power and three serial buses:
-UART, I2C, and SPI separately over 10 pins in a 2x5 layout.
+UART, I2C, and [[SPI]] separately over 10 pins in a 2x5 layout.
 [http://en.wikipedia.org/wiki/UEXT Wikipedia: UEXT]
 == BlackNet ==
@@ Line 161: / Line 185: @@
 is also electrically the same signals as the IBM PC/AT,
 but with a different physical hardware -- PATA uses ribbon-cables and square header pins.
@@ Line 210: / Line 240: @@
 * What expansion bus does the [https://hackaday.io/project/6025-skajntt "SkajNätt: An expandable computer system"] use?
 * [https://www.computer.org/csdl/magazine/mi/1984/03/04071079/13rRUx0gebd "IEEE Micro: P959 I/O Expansion Bus Proposed Standard"].

@@ Line 15: / Line 15: @@
 of the address bus, the data bus, and the control bus,
 and often also includes multiple pins dedicated to ground and power rails.
 Later systems generally separate high-speed stuff
@@ Line 39: / Line 97: @@
 Universal EXTension (UEXT) is a connector layout which includes power and three serial buses:
-Asynchronous, I2C, and SPI separately over 10 pins in a 2x5 layout.
+UART, I2C, and SPI separately over 10 pins in a 2x5 layout.
 == RC2014 bus ==
@@ Line 118: / Line 194: @@
 == Related ==
 * [[Minimig Expansion]]
 * [[Multi-purpose Embedded System]]
@@ Line 123: / Line 200: @@
 * [[Modules]]
 * [https://github.com/tpycio/Backplane4 "Backplane 4+1 for RCBus"]
 * [https://hackaday.io/project/183266-baffa-2-homebrew-microcomputer BAFFA backplane]
@@ Line 131: / Line 209: @@
 * "Bread-Board friendly Q-bus extended" or BBQ-bus+" used by the [https://hackaday.io/project/67369-pdpii "PDPii PDP-11 compatible motherboard"] ?
 * What expansion bus does the [https://hackaday.io/project/6025-skajntt "SkajNätt: An expandable computer system"] use?