Minimig Board v1.0 schematic

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Revision as of 17:38, 5 August 2007 by Freqmax (talk | contribs) (additional data)
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Board schematic for Minimig board v1.0

Audio output via 3,5mm jack

Voltage level: (3.3V/(560ohm + 560ohm + 32ohm))*32 ohm*1000 = 91,7mV
Back EMF issues?
Head phones

4 bit resistor ladder D/A

Notice the resistor of 560 ohm. May cause inlinear output.

in 15kHz mode:
/VSYNC = high (scart RGB enable)
/HSYNC = composite sync
IC5 FPGA Xilinx XC3S400-4PQ208C
IC3/IC4 FPGA core power +1,25V +2,5V using LM1117MP-ADJ
Joystick 0
Joystick 1
Program & Menu button, 31/15kHz selection, Power & Disc led
Keyboard & Mouse connections
MC68000
MC68000 Decoupling
Generation of 4.433619 MHz PAL video MCLK using 74HC4060 (NTSC=3.579545MHz)

PATCH needed to get rev 1 board working:

Disconnect net SPI_DOUT from pin 81 of FPGA.
Connect net SPI_DOUT to pin 19 of FPGA (net USER3).
REASON:
Pin 81 is an output during FPGA config that blocks SPI to MMC during startup.
Asynchronous static ram 512 x 16 bit (2 chips)
Serial RS232 using MAX232
Main power supply
SD Card slot
Spare I/O directly connected to FPGA



Xilinx ISE Webpack device support