Difference between revisions of "Minimig Board v1.0 MC68000 CPU connections"

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[[Image:Minimig_v10_board_m68k.png|thumb|right|250px|IC9 - MC68000]]
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[[Image:Minimig_v10_board_m68k.png|thumb| none |250px|IC9 - MC68000]]

Revision as of 16:11, 24 August 2007

IC9 - MC68000

Pin Name Assignment Comment
1 R/W R/W
2 nDTACK nDTACK
3 nBG
4 nBR Vcc
5 Vcc
6 CLK CPU_CLK
7 GND
8 MODE Vcc
9 nHALT nCPU_RST Wired via R68 2K2 resistor
10 nRESET nCPU_RST Wired via R67 2K2 resistor
11 nAVEC Vcc
12 nBERR Vcc
13 nIPL2 nIPL2
14 nIPL1 nIPL1
15 nIPL0 nIPL0
16 FC2
17 FC1
18 FC0
19 A0
20 A1 CPU_A1
21 A2 CPU_A2
22 A3 CPU_A3
23 GND
24 A4 CPU_A4
25 A5 CPU_A5
26 A6 CPU_A6
27 A7 CPU_A7
28 A8 CPU_A8
29 A9 CPU_A9
30 A10 CPU_A10
31 A11 CPU_A11
32 A12 CPU_A12
33 A13 CPU_A13
34 A14 CPU_A14
35 A15 CPU_A15
36 A16 CPU_A16
37 A17 CPU_A17
38 A18 CPU_A18
39 A19 CPU_A19
40 A20 CPU_A20
41 Vcc
42 A21 CPU_A21
43 A22 CPU_A22
44 A23 CPU_A23
45 D15 CPU_D15
46 D14 CPU_D14
47 D13 CPU_D13
48 D12 CPU_D12
49 D11 CPU_D11
50 D10 CPU_D10
51 D9 CPU_D9
52 D8 CPU_D8
53 D7 CPU_D7
54 D6 CPU_D6
55 D5 CPU_D5
56 GND
57 D4 CPU_D4
58 D3 CPU_D3
59 D2 CPU_D2
60 D1 CPU_D1
61 D0 CPU_D0
62 nAS nAS
63 nUDS nUDS
64 nLDS nLDS
IC9 - MC68000