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Test Action Group (JTAG) standardized a 5 pin boundary-scan test port as IEEE Std. 1149.1, "Standard Test Access Port and Boundary-Scan Architecture".
| + | The Joint Test Action Group (JTAG) standardized a 5 signal boundary-scan test port as IEEE Std. 1149.1, "Standard Test Access Port and Boundary-Scan Architecture". |
| | | | |
| | While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging. | | While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging. |
| Line 5: |
Line 5: |
| | [http://hogyros.de/?q=node/167 "If you have information on how to connect a JTAG probe to a Nokia phone, please let me know."] | | [http://hogyros.de/?q=node/167 "If you have information on how to connect a JTAG probe to a Nokia phone, please let me know."] |
| | | | |
| − | There are five pins: | + | There are five signals: |
| | * TCK/clock | | * TCK/clock |
| | * TMS/mode select | | * TMS/mode select |
| Line 19: |
Line 19: |
| | == 20 Pin JTAG PinOut == | | == 20 Pin JTAG PinOut == |
| | | | |
| − | Which one of these is right?
| + | 1 +3.3 V 2 +3.3 V |
| − | | |
| − | Pin Function Pin Function
| |
| − | 1 TRST 2 GND
| |
| − | 3 TDO 4 GND
| |
| − | 5 TDI 6 GND
| |
| − | 7 TMS 8 GND
| |
| − | 9 TCK 10 GND
| |
| − | 11 VPP_E 12 GND
| |
| − | 13 A/W 14 GND
| |
| − | 15 User 0 16 GND
| |
| − | 17 Rdy/Bsy 18 GND
| |
| − | 19 User 1 20 Vcc
| |
| − | | |
| − | 1 3.3 V 2 3.3 V | |
| | 3 nTRST 4 GND | | 3 nTRST 4 GND |
| | 5 TDI 6 GND | | 5 TDI 6 GND |
| Line 42: |
Line 28: |
| | 15 nRST 16 GND | | 15 nRST 16 GND |
| | 17 -- 18 GND | | 17 -- 18 GND |
| − | 19 -- 20 GND | + | 19 -- 20 GND |
| − | | |
| | | | |
| | == external links == | | == external links == |
| Line 50: |
Line 35: |
| | * [http://www.arm.com/support/faqdev/1336.html "When designing development boards what style JTAG connector should I use?"] The 20-pin JTAG connector. | | * [http://www.arm.com/support/faqdev/1336.html "When designing development boards what style JTAG connector should I use?"] The 20-pin JTAG connector. |
| | * [http://www.embedded.com/story/OEG20021028S0049 "Introduction to JTAG"] by Rob Oshana 2002 | | * [http://www.embedded.com/story/OEG20021028S0049 "Introduction to JTAG"] by Rob Oshana 2002 |
| − | * [http://hri.sourceforge.net/tools/jtag_faq_org.html "JTAG FAQ"] by Stas Khirman 2004 | + | * [http://hri.sourceforge.net/tools/jtag_faq_org.html "JTAG FAQ"] by Stas Khirman 2004 includes a section on [http://hri.sourceforge.net/tools/jtag_faq_org.html#_Toc63218715 14 pin, 20 pin, and 8 pin JTAG headers] |
| | * [http://k9spud.com/jtag/ a parallel port JTAG Debugger circuit for Philips LPC2xxx ARM microcontrollers.] by K9JTAG (uses Schmitt trigger inverters, so it can connect 3.0 V target boards to a standard 5.0 V parallel port) | | * [http://k9spud.com/jtag/ a parallel port JTAG Debugger circuit for Philips LPC2xxx ARM microcontrollers.] by K9JTAG (uses Schmitt trigger inverters, so it can connect 3.0 V target boards to a standard 5.0 V parallel port) |
| | * [http://diygadget.com/store/building-simple-jtag-cable/info_12.html parallel port JTAG "Building Simple JTAG Cable"] (resistors only) | | * [http://diygadget.com/store/building-simple-jtag-cable/info_12.html parallel port JTAG "Building Simple JTAG Cable"] (resistors only) |
| Line 59: |
Line 44: |
| | * [http://freelabs.com/~whitis/electronics/jtag/ the JTAG protocol] by Mark Whitis | | * [http://freelabs.com/~whitis/electronics/jtag/ the JTAG protocol] by Mark Whitis |
| | * [http://scienceprog.com/avrjtag-clone-in-action/ "Building AVR Jtag clone"] includes schematics and firmware. | | * [http://scienceprog.com/avrjtag-clone-in-action/ "Building AVR Jtag clone"] includes schematics and firmware. |
| − | | + | * [http://www.embecosm.com/ Embecosm] publishes a "SystemC JTAG interface specification" to simplify debugging complex chips. |
| | + | * lists a variety of [http://www.freelabs.com/~whitis/electronics/jtag/ JTAG Pinouts] |
| | + | * [http://tree.celinuxforum.org/CelfPubWiki/ELC2009Presentations?action=AttachFile&do=get&target=DebuggingWithJtagCelf2009.pdf Debugging with JTAG (CELF presentation)] |
| | + | * Open JTAG Project [http://www.openjtag.org Make your proper high speed JTAG] |
| | ---- | | ---- |
The Joint Test Action Group (JTAG) standardized a 5 signal boundary-scan test port as IEEE Std. 1149.1, "Standard Test Access Port and Boundary-Scan Architecture".
While originally intended for boundary-scan testing of PCB assemblies, to replace bed-of-nails testing, the JTAG port included in many popular microprocessors is also often used for programming and debugging.
"If you have information on how to connect a JTAG probe to a Nokia phone, please let me know."
There are five signals:
- TCK/clock
- TMS/mode select
- TDI/data in
- TDO/data out
- TRST/reset (optional), when driven low, resets the internal state machine.
Except for TCK, all other JTAG lines should be pulled high via a resistor.
WARNING: unconfirmed pinout. Please add links to pinout standard.
20 Pin JTAG PinOut[edit]
1 +3.3 V 2 +3.3 V
3 nTRST 4 GND
5 TDI 6 GND
7 TMS 8 GND
9 TCK 10 GND
11 -- 12 GND
13 TDO 14 GND
15 nRST 16 GND
17 -- 18 GND
19 -- 20 GND
external links[edit]
