Minimig NTSC fix code0 minimig1.v

//Master clock generator for minimig //This module generates all necessary clock from the 3.579545 NTSC clock module clock_generator(mclk,c_28m,c_7m,cq_7m,e); input mclk;                    //3.579545 MHz master oscillator input output c_28m;                  //28.63636 MHz clock out output c_7m;                   //7.15909  MHz  clock out output cq_7m;                  //7.15909  MHz  qudrature clock out output e;                      //0.715909  MHz clock enable out

reg ic_14m;                    //14.31818 MHz intermediate frequency reg ic_7m; reg icq_7m;

reg    [3:0]ediv;              //used to generate e clock enable

// Instantiate the DCM module // the DCM is configured to generator c_28m from mclk (multiply by 8) clock_dcm dcm1(   .CLKIN_IN(mclk),     .RST_IN(1'b0),     .CLKFX_OUT(c_28m),     .CLKIN_IBUFG_OUT,     .LOCKED_OUT    );

//generator ic_14m always @(posedge c_28m) ic_14m<=~ic_14m;

//generate ic_7m always @(posedge ic_14m) ic_7m<=~ic_7m;

//generate icq_7m always @(negedge ic_14m) icq_7m<=ic_7m;

//generate e always @(posedge c_7m) if(e) ediv<=9; else ediv<=ediv-1; assign e=(ediv==4'b0000)?1:0;

//clock buffers BUFG buf1 (    .I(ic_7m),                .O(c_7m) ); BUFG buf2 (    .I(icq_7m),                .O(cq_7m));

endmodule