Minimig Board v1.0 signaling

minimig1_firmware_15_07_2007/hardware.h
 * MCU: _F_CSx = FPGA spix select


 * {| class="wikitable"

! Signal !! MCU Pin !! MCU Name !! FPGA pin !! FPGA name !! Description
 * /FPGA_SEL0 || 3 || RA1 || 93 || IO           || EnableFpga _F_CS0=0
 * /FPGA_SEL1 || 26 || RB5 || 86 || IO_L30P_4/D3 || EnableOsd _F_CS1=0
 * /FPGA_SEL2 || 27 || RB6 || 87 || IO_L30N_4/D2 ||
 * }
 * /FPGA_SEL2 || 27 || RB6 || 87 || IO_L30N_4/D2 ||
 * }
 * }

FPGA <-> MCU interface consist of:
 * {| class="wikitable"

! Signal !! MCU dir !! SD/MMC dir !! FPGA dir !! Description
 * SPI_CLK || Out || In  || In || Clock
 * SPI_DIN || Out || In  || In || Data
 * SPI_DOUT || In || Out || Out || Data
 * }
 * SPI_DOUT || In || Out || Out || Data
 * }
 * }