Xilinx XC3S500E

Xilinx XC3S500E is logic optimized FPGA. Xilinx XC3S500E pins Xilinx XC3S500E pin description Xilinx Spartan-3E Datasheet

Default I/O standard for configuration: LVCMOS25 By setting VCCO_2 to another value, one can use 1,8V or 3,3V operation aswell.