RTL m68k

Is there a "soft core" m68k for FPGAs?

Haveing the cpu in vhdl/verilog would allow to eliminate the need for a special Minimig board. And being able to use plain developer boards from Xilinx or other manufactors.

Have you seen the discussion at Open Cores?

The most finished 68000 in VHDL I know of is from the Atari ST in VHDL: Suska project : 68000 IP v2K7A


 * Would it make any sense to replace the "FPGA chip + CPU chip" on the current Minimig, with a single-chip "FPGA + CPU chip" device? --DavidCary 21:28, 28 July 2007 (PDT)

The Plus Too project is a working hardware replica of the Macintosh Plus and Macintosh 512Ke computers. The project’s goal is to recreate these classic computers using modern electronic components, producing a stand-alone machine able to run period Macintosh software from the mid-1980′s. It replaces the original Motorola 68000 CPU with a soft-CPU module within a FPGA (although a future version will probably use a real 68000 CPU). It replaces the original floppy drives with a SD card interface.

The FPGA HP98x6 project includes a 68000 soft core.

TobiFlex 070826 13:39 This CPU Core is not finish. The Debuging must go on. Currently hangs up this CPU Core with Kickstartrom 2.04 at #$F81914.

TobiFlex 070826 14:06 I have adapted the minimig Core to the DE2 Board from Terasic with a ALTERA Cyclone 2C35. With an external CPU MC68HC000 runs the Minimig perfekt. I have change the RAM Timing from SRAM to SDRAM - so i can use the on Board SDRAM Chip. And now i use the Board to Debug Wolfgangs 68K Core.

mongo 070826 20:25 Wolfgang's 68K core will run up to about 17 MHz in a Spartan 3.

jkonstan 070826 21:23 external CBT16245 level shifters

TobiFlex 071126 13:49
 * TobiFlex releases his TG68 MC68000 project source code in VHDL. With a size of 3000 lines.
 * "The Kernal is 2x-3x faster then the 68000 with the same clock and you can clock them with 28MHz.

I think it is possible to make the minimig 8x-12x faster then the original."
 * Is there any attempt to make the instruction timings the same as the original 68k?
 * Most of the byte and word instructions are exact. Long and mulu/divu/rotation instructions are faster.


 * The MC68EC000 is different from the 68000. I have my Core let run against a real MC68HC000 and can not :find software differences when the Kickstart or some programms are running. So I know all importand :Instructions works correct. About never used Instructions I can not say anything.
 * Example: I have found no program for the AMIGA that use CHK or MOVEP Instructions.


 * About the doc on the second link. My Core use no prefetch. My Core use classical Fetch/Execute last - :Decode - Fetch next/Execute - order.
 * Thats why most Instrucions can execute in 2 clocks. The Bus wrapper expand this to 4 clocks.
 * But for the minimig is the prefetch not so important. The core is fast enough to decode the opcode between as=high. So the timing is the same as the 68000 timing.


 * On my DE2 Board with a real MC68EC000 and running ANARCHY1 DEMO I can see some rendering error but with the softcore I can not.
 * I dont know what happens but I think my core has a high Betatested Level. (Upss I hope you can understood my - sorry for my poor english)


 * OPCODE 0x0F0E MOVEP.W ..... My Validator stop here.

Boards:
 * http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=83
 * http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html

billt 071126 15:57
 * Simulators
 * http://www.symphonyeda.com/proddownloads.htm
 * http://ghdl.free.fr/
 * http://freehdl.seul.org/

alexh 071126 16:14
 * There are some subtle undocumented 68k behaviour that you might be interested in:
 * http://www.trzy.org/files/68knotes.txt
 * http://pasti.fxatari.com/68kdocs/
 * Testdisc known to be sensitive to 68000 incompatibility: http://amiga.nvg.org/warlock/adf/b/Birk+Sundell/100C64Tunes.adf.gz

Dennis 071126 19:48
 * Quick compile using webpack 6.3.03i:
 * Device utilization summary:
 * Selected Device : 3s400pq208-4
 * Number of Slices: 2627 out of 3584 73%
 * Number of Slice Flip Flops: 1052 out of 7168 14%
 * Number of 4 input LUTs: 4841 out of 7168 67%
 * Number of bonded IOBs: 74 out of 141 52%
 * Number of GCLKs: 1 out of 8 12%
 * Number of 4 input LUTs: 4841 out of 7168 67%
 * Number of bonded IOBs: 74 out of 141 52%
 * Number of GCLKs: 1 out of 8 12%


 * TIMING REPORT
 * TIMING REPORT


 * NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.


 * Timing Summary:
 * Speed Grade: -4
 * Speed Grade: -4


 * Minimum period: 39.906ns (Maximum Frequency: 25.059MHz)
 * Minimum input arrival time before clock: 16.900ns
 * Maximum output required time after clock: 16.576ns
 * Maximum combinational path delay: No path found


 * I need a bigger FPGA :-)

karsten 071126 20:02
 * Days of Thunder uses the CHK instruction: http://eab.abime.net/showthread.php?t=1144