Minimig 68K CPU BERR* Support

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We can connect one of the spare FPGA pins (such as USER I/O 3) to BERR* on the MC68SEC000 so that we can generate a Bus error exception to 68K CPU when bad code addresses non-existant memory. A Verilog code module to implement this function would be simple (equivalent to a single 74LCX164 or about 5 to 10 lines of Verilog in the Spartan3). I think that the Guru meditation Errors from Amiga OS support reporting BERR* Vector.

M68k bus cycle seems to be like this:

CPU activates AS* (Address strobe)
A valid device will respond by activating DTACK* (Data transfer acknowledge)
If there's no device a timeout circuit will activate BERR* (Bus error). Such that the cpu knows there's nothing there.

MC68SEC000 Datasheet on 68K bus cycle (S0-S9)

STATE 4 (S4)

During STATE4 (S4), the SCM68000 waits for a cycle termination signal (DTACKB or BERRB) If neither termination signal is asserted before the falling edge at the end of S4, the SCM68000 inserts wait states (full clock cycles) until either DTACKB or BERRB is asserted.

Without a BUS ERROR/BERR* circuit, a DTACK* would always have to be supplied to 68K when addressing non-existant memory via the external address decoder & DTACK* (wait state cycle) circuits; otherwise, 68K CPU will hang in the current bus cycle forever.

It seems BERR is not stricly needed. I presume current implementation happily answers any address with DTACK :-) Is there any software that (ab)use BERR?

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